The present invention relates to a duty factor control circuit suitable for use in an optical disk apparatus, particularly for a recording/reproducing circuit in an optical disk drive device of sample servo type.
FIG. 1 shows recorded patterns on the tracks of an optical disk. Each sector of the optical disk includes plural servo blocks (e.g., 43 servo blocks). One servo block includes a preformat portion composed of a servobyte of two bytes and a recording portion succeeding thereto composed of a data-byte of 16 bytes. The servobyte includes a clock pit and two wobbled pits located to the right and left with respect to the center of the track. A tracking error signal is generated in response to a detection signal of the two wobbled pits, and a clock signal is generated in response to a detection signal of the clock pit. Data are recorded on or reproduced from the disk, synchronously with the clock produced by the clock pit.
FIG. 2 is a block diagram of a conventional waveform shaping circuit in an optical disk apparatus. A pickup 1 reproduces a signal recorded on an optical disk (not shown) and puts out the reproduced (RF) signal. When the pickup encounters a pit on the surface of the optical disk, as shown in FIG. 3A, the level of the RF signal is lowered, as shown in FIG. 3B. A differentiation circuit 2 differentiates the RF signal applied from the pickup 1, and provides an output as shown in FIG. 3C. A detection circuit 3 detects a zero crossing of the output of the differentiation circuit 2 and produces a corresponding pulse, as shown in FIG. 3D. The pulse, which has a predetermined width and starts from the zero crossing point, is applied to a duty factor control circuit.
FIG. 4 is a block diagram showing a conventional duty factor control circuit. If a pulse as shown in FIG. 5B (corresponding to the pulse of FIG. 3D) is applied to the duty factor control circuit in synchronism with a clock produced by the clock pit on the disk as shown in FIG. 5A (in this case, a falling edge of a clock pulse is positioned at a center of the pulse width), the input pulse is delayed by a delay circuit 5 by a predetermined period of time, so that a delayed pulse is generated, as shown in FIG. 5C. The input pulse and the delayed pulse are applied to an AND gate 4 and an OR gate 6. As a result, pulses each having a width (and therefore a duty factor) different from the input pulse are produced at the outputs (d) and (e) as shown in the waveform diagrams of FIGS. 5D and 5E, respectively.
However, in the conventional duty factor control circuit, either a leading or a trailing edge of an input pulse may be varied, while the other edge remains fixed, so that the center of an output pulse does not coincide with an edge of a clock pulse. The result can cause what is known as a time base error. As a result, for example, when a level (H or L) of an output pulse is read in accordance with the timing of the falling edge of a clock pulse, the time base error can influence the operation of the duty factor control circuit depending on the direction of the error.
The duty factor control circuit of FIG. 4 is used not only in a disk reproducing circuit as described above, but also used in a disk recording circuit. In the case where the duty factor control circuit is used in a disk recording circuit, if the center of the duty factor controlled data pulse to be recorded on the disk does not coincide with an edge of a clock pulse there is the same problem as that occurs in the disk reproducing circuit described already.
The problem which occurs in the case where the center of the duty factor controlled data pulse does not coincide with the edge of the clock pulse will be discussed below with reference to FIG. 6. The description is made, for example, about the case where the duty factor control circuit of FIG. 4 is used in a data recording circuit.
If a data pulse to be recorded as shown in FIG. 6B is applied to the duty factor control circuit of FIG. 4 in synchronism with a clock as shown in FIG. 6A (in this case, a falling edge of a clock pulse is positioned at a center of the pulse width), the data pulse is delayed by a delay circuit 5 by a predetermined period of time, so that a delayed pulse is generated, as shown in FIG. 6C. The data pulse and the delayed pulse are applied to an AND gate 4 and an OR gate 6. As a result, pulses each having a width (and therefore a duty factor) different from the data pulse are produced at the outputs (d) and (e) as shown in the waveform diagrams of FIGS. 6D and 6E, respectively. If the pulse of FIG. 6D is used, the pulse forms a pit as shown in FIG. 6F on the disk. On the other hand, if the pulse of FIG. 6E is used, the pulse forms a pit as shown in FIG. 6G on the disk.
When reproducing the pit shown in FIG. 6F (or 6G) on the disk, a level (H or L) of a reproducing signal shown in FIG. 6H (or 6I) is read in accordance with the timing of the edge (e.g., a falling edge) of a clock pulse. In this case, jitter (time axis deviation) is occurred, the reading timing is deviated. In accordance with the direction of the deviation, the probability of such an error that the L(H) level will be erroneously read as an H(L) level becomes high.